The present invention relates to integrated circuit (semiconductor) memory devices and methods of fabricating the same, more particularly, to semiconductor memory devices which are capable of obtaining a process margin with improved electrical characteristics, and methods of fabricating the same.
For integrated circuit (semiconductor) devices requiring a high speed of operation, an associated design rule may be reduced. As the design rule is reduced, a RC delay effect on device performance may increase due to an increase of the resistance and the capacitance of a wiring line formed on the device. This increase RC delay may, in turn, lower the operating speed of the device.
In order to address the RC delay problem, it is know to use an interlayer insulating layer having a lower dielectric rate and wiring line materials having a lower resistance. For example, copper (Cu), rather than aluminum alloy, may be used as a wiring line material, as copper has lower specific resistance than the conventional aluminum alloy. In addition, copper typically has a smaller electrical migration than the conventional aluminum alloy.
However, when forming wiring lines using copper, as the etching characteristic of copper is generally very poor compared to aluminum, the wiring line is generally formed by a damascene process. A dual damascene process, which forms a via and a trench in the interlayer insulating layer and forms the wiring line by burying copper in the via and the trench has been used as a damascene process.
In the dual damascene process, when forming the via and the trench, a method of forming the trench after formation of the via may be used. However, in the course of forming the trench after formation of the via, a corner of the via may collapse, thereby generated a sloped region in the via. As a result, the lower wiring line may be exposed, which may cause the lower wiring line and an upper wiring line to be shorted.